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rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adg428/adg429 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 functional block diagrams lc 2 mos latchable 4-/8-channel high performance analog multiplexers features 44 v supply maximum ratings v ss to v dd analog signal range low on resistance (60 v typ) low power consumption (1.6 mw max) low charge injection (<4 pc typ) fast switching break-before-make switching action plug-in replacement for dg428/dg429 applications automatic test equipment data acquisition systems communication systems avionics and military systems microprocessor controlled analog systems medical instrumentation general description the adg428 and adg429 are monolithic cmos analog multiplexers comprising eight single channels and four differen- tial channels respectively. on-chip address and control latches facilitate microprocessor interfacing. the adg428 switches one of eight inputs to a common output as determined by the 3-bit binary address lines a0, a1 and a2. the adg429 switches one of four differential inputs to a common differential output as determined by the 2-bit binary address lines a0 and a1. an en input on both devices is used to enable or disable the device. when disabled, all channels are switched off. all the control inputs, address and enable inputs are ttl compatible over the full specified operating temperature range. this makes the part suitable for bus-controlled systems such as data acquisition sys- tems, process controls, avionics and ates because the ttl- compatible address latches simplify the digital interface design and reduce the board space required. the adg428/adg429 are designed on an enhanced lc 2 mos process that provides low power dissipation yet gives high switching speed and low on resistance. each channel conducts equally well in both directions when on and has an input signal range that extends to the supplies. in the off condition, signal levels up to the supplies are blocked. all channels exhibit break-before-make switching action, preventing momentary shorting when switching channels. inherent in the design is low charge injection for mini- mum transients when switching the digital inputs. the adg428/adg429 are improved replacements for the dg428/dg429 analog multiplexers. product highlights 1. extended signal range the adg428/adg429 are fabricated on an enhanced lc 2 mos process, giving an increased signal range that ex- tends to the supply rails. 2. low power dissipation 3. low r on 4. single/dual supply operation 5. single supply operation for applications where the analog signal is unipolar, the adg428/adg429 can be operated from a single rail power supply. the parts are fully specified with a single +12 v power supply and will remain functional with single supplies as low as +5 v. adg428 decoders/drivers latches wr s1 s8 rs d a2 a1 a0 en da s1a s4a adg429 decoders/drivers a1 a0 en db s1b s4b latches wr rs obsolete
rev. c C2C adg428/adg429Cspecifications dual supply 1 b version t version C40 8 c to C55 8 c to parameter +25 8 c +85 8 c +25 8 c +125 8 c units test conditions/comments analog switch analog signal range v ss to v dd v ss to v dd v r on 60 60 w typ v d = 10 v, i s = C1 ma 100 125 100 125 w max d r on 10 10 % max C10 v < v s < 10 v, i s = C1 ma leakage currents source off leakage i s (off) 0.03 0.3 0.03 0.3 na typ v d = 10 v, v s = 7 10 v; 0.5 50 0.5 50 na max test circuit 2 drain off leakage i d (off) v d = 10 v, v s = 7 10 v; adg428 0.07 0.7 0.07 0.7 na typ test circuit 3 1 100 1 100 na max adg429 0.05 0.5 0.05 0.5 na typ 1 50 1 50 na max channel on leakage i d , i s (on) v s = v d = 10 v; adg428 1 100 1 100 na max test circuit 4 adg429 1 50 1 50 na max digital inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.8 0.8 v max input current i inl or i inh 0.1 1 0.1 1 m a max v in = 0 or v dd c in , digital input capacitance 8 8 pf typ f = 1 mhz dynamic characteristics 2 t transition 110 110 ns typ r l = 1 m w , c l = 35 pf; 250 300 250 300 ns max v s1 = 10 v, v s8 = 7 10 v; test circuit 5 t open 10 10 ns min r l = 1 k w , c l = 35 pf; v s = +5 v; test circuit 6 t on (en, wr ) 115 115 ns typ r l = 1 k w , c l = 35 pf; 150 225 150 225 ns max v s = +5 v; test circuit 7 t off (en, rs ) 105 105 ns typ r l = 1 k w , c l = 35 pf; 150 300 150 300 ns max v s = +5 v; test circuit 7 t w , write pulsewidth 100 100 ns min t s , address, enable setup time 100 100 ns min t h , address, enable hold time 10 10 ns min t rs , reset pulsewidth 100 100 ns min v s = +5 v charge injection 4 4 pc typ v s = 0 v, r s = 0 w , c l = 10 nf; test circuit 10 off isolation C75 C75 db typ r l = 1 k w , c l = 15 pf, f = 100 khz; C60 C60 db min v s = 7 v rms, v en = 0 v; test circuit 11 channel-to-channel crosstalk 85 85 db typ r l = 1 k w , c l = 15 pf, f = 100 khz; test circuit 12 c s (off) 11 11 pf typ f = 1 mhz c d (off) f = 1 mhz adg428 40 40 pf typ adg429 20 20 pf typ c d , c s (on) f = 1 mhz adg428 54 54 pf typ adg429 34 34 pf typ power requirements v in = 0 v, v en = 0 v i dd 20 20 m a typ 100 100 m a max i ss 0.001 0.001 m a typ 55 m a max notes 1 temperature ranges are as follows: b version: C40 c to +85 c; t version: C55 c to +125 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. (v dd = +15 v, v ss = C15 v, gnd = 0 v, wr = 0 v, rs = 2.4 v unless otherwise noted) obsolete
rev. c C3C adg428/adg429 single supply 1 b version t version C40 8 c to C55 8 c to parameter +25 8 c +85 8 c +25 8 c +125 8 c units test conditions/comments analog switch analog signal range 0 to v dd 0 to v dd v r on 90 90 w typ v d = +10 v, i s = C500 m a 200 200 w max d r on 10 10 % max 0 v < v s < 10 v, i s = C1 ma leakage currents source off leakage i s (off) 0.005 0.005 na typ v d = 10 v/0 v, v s = 0 v/10 v; 0.5 50 0.5 50 na max test circuit 2 drain off leakage i d (off) v d = 10 v/0 v, v s = 0 v/10 v; adg428 0.015 0.015 na typ test circuit 3 1 100 1 100 na max adg429 0.008 0.008 na typ 1 50 1 50 na max channel on leakage i d , i s (on) v s = v d = 10 v/0 v; adg428 0.02 0.02 na typ test circuit 4 1 100 1 100 na max adg429 0.01 0.01 na max 1 50 1 50 na max digital inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.8 0.8 v max input current i inl or i inh 1 1 m a max v in = 0 or v dd c in , digital input capacitance 8 8 pf typ f = 1 mhz dynamic characteristics 2 t transition 250 250 ns typ r l = 1 m w , c l = 35 pf; 350 450 350 450 ns max v s1 = 10 v/0 v, v s8 = 0 v/10 v; test circuit 5 t open 25 10 25 10 ns min r l = 1 k w , c l = 35 pf; v s = +5 v; test circuit 6 t on (en, wr ) 200 200 ns typ r l = 1 k w , c l = 35 pf; 300 400 300 400 ns max v s = +5 v; test circuit 7 t off (en, rs ) 80 80 ns typ r l = 1 k w , c l = 35 pf; 300 400 300 400 ns max v s = +5 v; test circuit 7 t w , write pulsewidth 100 100 ns min t s , address, enable setup time 100 100 ns min t h , address, enable hold time 10 10 ns min t rs , reset pulsewidth 100 100 ns min v s = +5 v charge injection 4 4 pc typ v s = 6 v, r s = 0 w , c l = 10 nf; test circuit 10 off isolation C75 C75 db typ r l = 1 k w , c l = 15 pf, f = 100 khz; C60 C60 db min v s = 7 v rms, v en = 0 v; test circuit 11 channel-to-channel crosstalk 85 85 db typ r l = 1 k w , c l = 15 pf, f = 100 khz; test circuit 12 c s (off) 11 11 pf typ f = 1 mhz c d (off) f = 1 mhz adg428 40 40 pf typ adg429 20 20 pf typ c d , c s (on) f = 1 mhz adg428 54 54 pf typ adg429 34 34 pf typ power requirements v in = 0 v, v en = 0 v i dd 20 20 m a typ 100 100 m a max notes 1 temperature ranges are as follows: b version: C40 c to +85 c; t version: C55 c to +125 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. (v dd = +12 v, v ss = 0 v, gnd = 0 v, wr = 0 v, rs = 2.4 v unless otherwise noted) obsolete
rev. c adg428/adg429 C4C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg428/adg429 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 (t a = +25 c unless otherwise noted.) v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +25 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to C25 v analog, digital inputs 2 . . . . . . . . . . v ss C 2 v to v dd + 2 v or 30 ma, whichever occurs first continuous current, s or d . . . . . . . . . . . . . . . . . . . . . 30 ma peak current, s or d . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ma (pulsed at 1 ms, 10% duty cycle max) operating temperature range industrial (b version) . . . . . . . . . . . . . . . . . C40 c to +85 c extended (t version) . . . . . . . . . . . . . . . . C55 c to +125 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 c cerdip package, power dissipation . . . . . . . . . . . . . . . 900 mw q ja , thermal impedance . . . . . . . . . . . . . . . . . . . . . 73 c/w lead temperature, soldering (10 sec) . . . . . . . . . . . +300 c plastic package, power dissipation . . . . . . . . . . . . . . . 470 mw q ja , thermal impedance . . . . . . . . . . . . . . . . . . . . 115 c/w lead temperature, soldering (10 sec) . . . . . . . . . . . +260 c soic package, power dissipation . . . . . . . . . . . . . . . . 600 mw q ja , thermal impedance . . . . . . . . . . . . . . . . . . . . . 77 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c plcc package, power dissipation . . . . . . . . . . . . . . . 800 mw q ja , thermal impedance . . . . . . . . . . . . . . . . . . . . . 90 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. 2 overvoltages at a, en, wr , rs , s or d will be clamped by internal diodes. current should be limited to the maximum ratings given. ordering guide model 1 temperature range package options 2 adg428bn C40 c to +85 c n-18 adg428bp C40 c to +85 c p-20a adg428br C40 c to +85 c r-18 adg428tq C55 c to +125 cq-18 adg429bn C40 c to +85 c n-18 adg429bp C40 c to +85 c p-20a adg429tq C55 c to +125 cq-18 notes 1 for availability of mil-std-883, class b processed parts, contact factory. 2 n = plastic dip; p = plastic leaded chip carrier (plcc); q = cerdip; r = small outline ic (soic). adg429 pin configurations dip/soic plcc top view (not to scale) 18 17 16 15 14 13 12 11 10 1 2 3 4 5 6 7 8 9 adg428 d s4 wr a0 en v ss s3 s2 s1 s8 s7 rs a1 a2 gnd s6 s5 v dd 3 2 1 20 19 9 10 11 12 13 18 17 16 15 14 4 5 6 7 8 top view (not to scale) pin 1 identifier nc = no connect en v ss s1 s2 s3 a2 gnd v dd s5 s6 adg428 a0 wr nc rs a1 s4 d nc s8 s7 dip plcc top view (not to scale) 18 17 16 15 14 13 12 11 10 1 2 3 4 5 6 7 8 9 adg429 da s4a wr a0 en v ss s3a s2a s1a db s4b rs a1 gnd v dd s3b s2b s1b 3 2 1 20 19 9 10 11 12 13 18 17 16 15 14 4 5 6 7 8 top view (not to scale) pin 1 identifier nc = no connect en v ss s1a s2a s3a gnd v dd s1b s2b s3b adg429 a0 wr nc rs a1 s4a da nc db s4b adg428 pin configurations obsolete
rev. c adg428/adg429 C5C adg428 truth table a2 a1 a0 en wr rs on switch latching xxxx g 1 maintains previous switch condition reset xxxxx0 none (latches cleared) transparent operation x x x 0 0 1 none 000101 1 001101 2 010101 3 011101 4 100101 5 101101 6 110101 7 111101 8 adg429 truth table a1 a0 en wr rs on switch pair latching xxx g 1 maintains previous switch condition reset xxxx0 none (latches cleared) transparent operation x x 0 0 1 none 001011 011012 101013 111014 terminology v dd most positive power supply potential. v ss most negative power supply potential in dual supplies. in single supply applications, it may be connected to ground. gnd ground (0 v) reference. r on ohmic resistance between d and s. d r on difference between the r on of any two channels. i s (off) source leakage current when the switch is off. i d (off) drain leakage current when the switch is off. i d , i s (on) channel leakage current when the switch is on. v d (v s ) analog voltage on terminals d, s. c s (off) channel input capacitance for off condition. c d (off) channel output capacitance for off condition. c d , c s (on) on switch capacitance. c in digital input capacitance. t on (en) delay time between the 50% and 90% points of the digital input and switch on condition. t off (en) delay time between the 50% and 90% points of the digital input and switch off condition. t transitlon delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. t open off time measured between 80% points of both switches when switching from one address state to another. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input. crosstalk a measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. off isolation a measure of unwanted signal coupling through an off channel. charge a measure of the glitch impulse transferred injection from the digital input to the analog output during switching. i dd positive supply current. i ss negative supply current. obsolete
rev. c adg428/adg429 C6C timing diagrams 3v wr 0v 3v a0, a1, (a2) en 0v 50% 50% t w t s t h 2v 0.8v figure 1. figure 1 shows the timing sequence for latching the switch address and enable inputs. the latches are level sensitive; there- fore, while wr is held low, the latches are transparent and the switches respond to the address and enable inputs. this input data is latched on the rising edge of wr . 50% 50% 3v rs 0v v o switch output 0v 0.8v o t rs t off ( rs ) figure 2. figure 2 shows the reset pulsewidth, t rs , and the reset turnoff time, t off , ( rs ). note: all digital input signals rise and fall times are measured from 10% to 90% of 3 v. tr = tf = 20 ns. typical characteristics v d (v s ) C volts 140 40 C15 15 C10 r on C v C5 0 5 10 130 100 70 80 v dd = +15v v ss = C15v 60 50 120 110 90 t a = +25 8 c v dd = +5v v ss = C5v v dd = +12v v ss = C12v v dd = +10v v ss = C10v figure 3. r on as a function of v d (v s ): dual supply voltage v d (v s ) C volts 80 40 r on C v 75 60 55 50 45 70 65 C15 15 C10 C5 0510 v dd = +15v v ss = C15v +125 8 c +85 8 c +25 8 c figure 4. r on as a function of v d (v s ) for different temperatures v d (v s ) C volts 600 550 100 015 36912 400 250 200 150 500 450 300 350 r on C v 50 0 t a = +25 8 c v dd = +12v v ss = 0v v dd = +10v v ss = 0v v dd = +5v v ss = 0v v dd = +15v v ss = 0v figure 5. r on as a function of v d (v s ): single supply voltage v d (v s ) C volts 160 60 015 2 r on C v 46810 150 120 90 80 70 140 130 110 100 v dd = +12v v ss = 0v +125 8 c +25 8 c +85 8 c figure 6. r on as a function of v d (v s ) for different temperatures obsolete
rev. c adg428/adg429 C7C switching frequency C hz 6000 1000 10 10m 100 i dd C m a 1k 10k 100k 1m 5500 4000 2500 2000 1500 5000 4500 3500 3000 500 0 v dd = +15v v ss = C15v en = 2.4v en = 0v figure 7. positive supply curr ent vs. switching f requency v in C volts 115 3 5 7 9 11 13 130 50 t C ns 120 90 80 70 60 110 100 v dd = +15v v ss = C15v t on (en) t transition t off (en) figure 8. switching time vs. v in (bipolar supply) v supply C volts 300 275 50 6 5 6 15 6 7 6 9 6 11 6 13 200 125 100 75 250 225 150 175 t C ns 25 0 v in = +5v t on (en) t transition t off (en) figure 9. switching time vs. bipolar supply v dd = +15v v ss = C15v switching frequency C hz 1000 100 0.1 10 10m 100 i ss C m a 1k 10k 100k 1m 10 1 en = 2.4v en = 0v figure 10. negative supply current vs. switching frequency v in C volts 200 40 t C ns 180 120 100 80 60 160 140 113 357911 t off (en) t transition t on (en) v dd = +12v v ss = 0v figure 11. switching time vs. v in (single supply) v supply C volts 500 200 0 515 6 t C ns 7 8 9 10 11 12 13 14 450 250 150 50 350 300 100 400 v in = +5v t on (en) t transition t off (en) figure 12. switching time vs. single supply obsolete
rev. c adg428/adg429 C8C frequency C hz 100 95 50 100 10m 1k 10k 100k 1m 80 65 60 55 90 85 70 75 off isolation C db 45 40 v dd = +15v v ss = C15v figure 13. off isolation vs. frequency v d (v s ) C volts 0.2 C0.1 C15 15 C10 leakage current C na C5 0 5 10 0.1 0 v dd = +15v v ss = C15v t a = +25 8 c i d (on) i d (off) i s (off) figure 14. leakage currents as a function of v d (v s ) frequency C hz 110 105 60 1k 10k 100k 90 75 70 65 100 95 80 85 crosstalk C db 55 50 v dd = +15v v ss = C15v 1m 10m figure 15. crosstalk vs. frequency v d (v s ) C volts 0.04 C0.04 leakage current C na 0.03 0 C0.01 C0.02 C0.03 0.02 0.01 012 246810 v dd = +12v v ss = 0v t a = +25 8 c i d (off) i s (off) i d (on) figure 16. leakage currents as a function of v d (v s ) obsolete
rev. c adg428/adg429 C9C test circuits i ds v1 sd v s r on = v1/i ds test circuit 1. on resistance s1 d s2 s8 a en gnd v dd v ss v dd v ss +0.8v v d v s i s (off) test circuit 2. i s (off) s1 d s2 s8 a en gnd v dd v ss v dd v ss +0.8v v d v s i d (off) test circuit 3. i d (off) s1 d s8 a en gnd v dd v ss v dd v ss 2.4v v d v s i d (on) test circuit 4. i d (on) v dd v ss v dd v ss v s1 v s8 output adg428* a0 a1 a2 50 v 2.4v en gnd s1 s2Cs7 s8 d 1m v 35pf *similar connection for adg429 rs v in wr 3v 0v enable drive C v in t transition t transition output 50% 50% 90% 90% test circuit 5. switching time of multiplexer, t transition v dd v ss v dd v ss v s output adg428* a0 a1 a2 50 v 2.4v en gnd s1 s2Cs7 s8 d 1k v 35pf *similar connection for adg429 rs v in wr 3v 0v address drive C v in output 80% 80% t open test circuit 6. break-before-make delay, t open obsolete
rev. c adg428/adg429 C10C v dd v ss v dd v ss v s output adg428* a0 a1 a2 2.4v en gnd s1 s2Cs8 d 1k v 35pf *similar connection for adg429 rs wr 50 v v in 3v 0v enable drive Cv in output (v o ) 0.9v o v o 0v 50% 50% 0.9v o t on (en) t off (en) test circuit 7. enable delay, t on (en), t off (en) v dd v ss v dd v ss v s output adg428* a0 a1 a2 2.4v en gnd s1 s2Cs8 d 1k v 35pf *similar connection for adg429 rs wr v rs v wr 3v 0v wr output v o 0v 50% 0.2v o t on ( wr ) test circuit 8. write turn-on time, t on (wr ) v dd v ss v dd v ss v s output adg428* a0 a1 a2 2.4v en s1 s2Cs8 d 1k v 35pf *similar connection for adg429 rs v in gnd wr 3v 0v rs output v o 0v 50% 0.8v o t off ( rs ) test circuit 9. reset turn-off time, t off ( rs ) obsolete
rev. c adg428/adg429 C11C v dd v ss v dd v ss v in adg428* a0 a1 a2 2.4v en d *similar connection for adg429 rs gnd wr c l 10nf s v s r s v out 3v en v out q inj = c l 3 d v out d v out test circuit 10. charge injection v dd v ss v dd v ss 2.4v adg428 a0 a1 a2 d rs en 1k v s1 v out s8 gnd wr v s 0v test circuit 11. off isolation v dd v ss v dd v ss 2.4v adg428 a0 a1 a2 d rs en 1k v s1 v out s2 s8 gnd wr 1k v v s test circuit 12. crosstalk obsolete
rev. c adg428/adg429 C12C outline dimensions dimensions shown in inches and (mm). c1825cC0C5/99 printed in u.s.a. plcc (p-20a) 3 pin 1 identifier 4 19 18 8 9 14 13 top view (pins down) 0.395 (10.02) 0.385 (9.78) sq 0.356 (9.04) 0.350 (8.89) sq 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.020 (0.50) r 0.050 (1.27) bsc 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.290 (7.37) 0.032 (0.81) 0.026 (0.66) 0.180 (4.57) 0.165 (4.19) 0.040 (1.01) 0.025 (0.64) 0.056 (1.42) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.110 (2.79) 0.085 (2.16) plastic dip (n-18) 18 19 10 0.910 ( 23.12 ) 0.890 (22.61) 0.260 (6.61) 0.240 (6.10) pin 1 seating plane 0.020 (0.508) 0.015 (0.381) 0.180 (4.48) max 0.065 (1.66) 0.045 (1.15) 0.175 (4.45) 0.120 (3.05) 0.105 (2.67) 0.095 (2.42) 0.306 (7.78) 0.294 (7.47) 0.120 (0.305) 0.008 (0.203) 0.140 (3.56) 0.120 (3.05) cerdip (q-18) 18 1 9 10 0.310 (7.87) 0.220 (5.59) pin 1 seating plane 0.022 (0.58) 0.014 (0.36) 0.200 (5.08) max 0.840 (21.34) max 0.150 (3.81) min 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 0.060 (1.52) 0.015 (0.38) 0.320 (8.13) 0.290 (7.37) 0.015 (0.381) 0.008 (0.204) soic (r-18) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 18 10 9 1 0.4625 (11.75) 0.4469 (11.35) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 obsolete

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